/*
 *  Copyright (c) 2022 ZhuHai Jieli Technology Co.,Ltd.
 *  Licensed under the Apache License, Version 2.0 (the "License");
 *  you may not use this file except in compliance with the License.
 *  You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 *  Unless required by applicable law or agreed to in writing, software
 *  distributed under the License is distributed on an "AS IS" BASIS,
 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the License for the specific language governing permissions and
 *  limitations under the License.
 */

// *********************************************************************************//
//  Module name : csfr.h                                                            //
//  Description : q32DSP core sfr define                                            //
//  By Designer : zequan_liu                                                        //
//  Dat changed :                                                                   //
// *********************************************************************************//

#ifndef __Q32DSP_CSFR__
#define __Q32DSP_CSFR__

#define __RW      volatile       // read write
#define __RO      volatile const // only read
#define __WO      volatile       // only write

#define __u8      unsigned int   // u8  to u32 special for struct
#define __u16     unsigned int   // u16 to u32 special for struct
#define __u32     unsigned int

// hcore_sfr
#define csfr_base    0x100000

// ............. 0x0100 - 0x01ff............
typedef struct {
    __RW __u32 CON;
    __RW __u32 KEY;
} JL_SDTAP_TypeDef;

#define JL_SDTAP_BASE                  (csfr_base + map_adr(0x01, 0x00))
#define JL_SDTAP                       ((JL_SDTAP_TypeDef *)JL_SDTAP_BASE)

// ............. 0x0200 - 0x02ff............
typedef struct {
    __RW __u32 MBISTCTL;
    __RO __u32 MBISTSOGO;
} JL_MBIS_TypeDef;

#define JL_MBIS_BASE                   (csfr_base + map_adr(0x02, 0x00))
#define JL_MBIS                        ((JL_MBIS_TypeDef *)JL_MBIS_BASE)

// ............. 0x0300 - 0x03ff............ for mmu

typedef struct {
    __RW __u32 CON;
    __RW __u32 TLB1_BEG;
    __RW __u32 TLB1_END;
} JL_MMU_TypeDef;

#define JL_MMU_BASE                  (csfr_base + map_adr(0x03, 0x00))
#define JL_MMU                       ((JL_MMU_TypeDef *)JL_MMU_BASE)

// ............. 0x1000 - 0x10ff............ for debug
typedef struct {
    __RW __u32 CON;
    __RW __u32 RING_OSC;
    __RW __u32 CPASS_CON;
    __RW __u32 CPASS_ADRH;
    __RW __u32 CPASS_ADRL;
    __RW __u32 CPASS_BUF_LAST;
    __RW __u32 CPREFETCH_ADRH;
    __RW __u32 CPREFETCH_ADRL;
    __RO __u32 CACHE_MSG_CH;
} JL_DSP_TypeDef;

#define JL_DSP_BASE                   (csfr_base + map_adr(0x10, 0x00))
#define JL_DSP                        ((JL_DSP_TypeDef*)JL_DSP_BASE)

typedef struct {
    __RW __u32 DSP_BF_CON;
    __RW __u32 WR_EN;
    __RO __u32 MSG;
    __WO __u32 MSG_CLR;
    __RW __u32 DSP_EX_LIMH;
    __RW __u32 DSP_EX_LIML;
    __RW __u32 PRP_EX_LIMH;
    __RW __u32 PRP_EX_LIML;
    __RO __u32 PRP_MMU_MSG;
    __RO __u32 LSB_MMU_MSG_CH;
    __RO __u32 PRP_WR_LIMIT_MSG;
    __RO __u32 LSB_WR_LIMIT_CH;
    __RW __u32 DSP_PC_LIMH0;
    __RW __u32 DSP_PC_LIML0;
    __RW __u32 DSP_PC_LIMH1;
    __RW __u32 DSP_PC_LIML1;
    __RW __u32 PRP_SRM_INV_MSG;
    __RW __u32 LSB_SRM_INV_CH;
} JL_DEBUG_TypeDef;

#define JL_DEBUG_BASE                 (csfr_base + map_adr(0x10, 0x10))
#define JL_DEBUG                      ((JL_DEBUG_TypeDef *)JL_DEBUG_BASE)

// ............. 0x2000 - 0x20ff............ for fft
typedef struct {
    __RW __u32 CON;
    __RW __u32 CADR;
    __RW __u32 TEST0;
    __RW __u32 TEST1;
} JL_FFT_TypeDef;

#define JL_FFT_BASE                  (csfr_base + map_adr(0x20, 0x00))
#define JL_FFT                       ((JL_FFT_TypeDef *)JL_FFT_BASE)

// q32DSP_sfr

// q32DSP define

#define q32DSP_sfr_offset   0x010000
#define q32DSP_sfr_base    (csfr_base + 0xf000)

#define q32DSP_cpu_base    (q32DSP_sfr_base + 0x00)
#define q32DSP_mpu_base    (q32DSP_sfr_base + 0x80)

#define q32DSP(n)          ((JL_TypeDef_q32DSP     *)(q32DSP_sfr_base + (q32DSP_sfr_offset)*n))
#define q32DSP_mpu(n)      ((JL_TypeDef_q32DSP_MPU *)(q32DSP_mpu_base + (q32DSP_sfr_offset)*n))

// q32DSP core sfr

typedef struct {
    __RO __u32 DR00; /* 00 */
    __RO __u32 DR01; /* 01 */
    __RO __u32 DR02; /* 02 */
    __RO __u32 DR03; /* 03 */
    __RO __u32 DR04; /* 04 */
    __RO __u32 DR05; /* 05 */
    __RO __u32 DR06; /* 06 */
    __RO __u32 DR07; /* 07 */
    __RO __u32 DR08; /* 08 */
    __RO __u32 DR09; /* 09 */
    __RO __u32 DR10; /* 0a */
    __RO __u32 DR11; /* 0b */
    __RO __u32 DR12; /* 0c */
    __RO __u32 DR13; /* 0d */
    __RO __u32 DR14; /* 0e */
    __RO __u32 DR15; /* 0f */

    __RO __u32 RETI; /* 10 */
    __RO __u32 RETE; /* 11 */
    __RO __u32 RETX; /* 12 */
    __RO __u32 RETS; /* 13 */
    __RO __u32 SR04; /* 14 */
    __RO __u32 PSR;  /* 15 */
    __RO __u32 CNUM; /* 16 */
    __RO __u32 SR07; /* 17 */
    __RO __u32 SR08; /* 18 */
    __RO __u32 SR09; /* 19 */
    __RO __u32 SR10; /* 1a */
    __RO __u32 ICFG; /* 1b */
    __RO __u32 USP;  /* 1c */
    __RO __u32 SSP;  /* 1d */
    __RO __u32 SP;   /* 1e */
    __RO __u32 PCRS; /* 1f */

    __RW __u32 BPCON;                      /* 20 */
    __RW __u32 BSP;                        /* 21 */
    __RW __u32 BP0;                        /* 22 */
    __RW __u32 BP1;                        /* 23 */
    __RW __u32 BP2;                        /* 24 */
    __RW __u32 BP3;                        /* 25 */
    __WO __u32 CMD_PAUSE;                  /* 26 */
    __RO __u32 REV_30_26[0x30 - 0x26 - 1];

    __RW __u32 PMU_CON;                     /* 30 */
    __RO __u32 REV_34_30[0x34 - 0x30 - 1];  /*    */
    __RW __u32 EMU_CON;                     /* 34 */
    __RW __u32 EMU_MSG;                     /* 35 */
    __RW __u32 EMU_SSP_H;                   /* 36 */
    __RW __u32 EMU_SSP_L;                   /* 37 */
    __RW __u32 EMU_USP_H;                   /* 38 */
    __RW __u32 EMU_USP_L;                   /* 39 */
    __RO __u32 REV_3b_39[0x3b - 0x39 - 1];  /*    */
    __RW __u8  TTMR_CON;                    /* 3b */
    __RW __u32 TTMR_CNT;                    /* 3c */
    __RW __u32 TTMR_PRD;                    /* 3d */
    __RW __u32 BANK_CON;                    /* 3e */
    __RW __u32 BANK_NUM;                    /* 3f */

    __RW __u32 ICFG00; /* 40 */
    __RW __u32 ICFG01; /* 41 */
    __RW __u32 ICFG02; /* 42 */
    __RW __u32 ICFG03; /* 43 */
    __RW __u32 ICFG04; /* 44 */
    __RW __u32 ICFG05; /* 45 */
    __RW __u32 ICFG06; /* 46 */
    __RW __u32 ICFG07; /* 47 */
    __RW __u32 ICFG08; /* 48 */
    __RW __u32 ICFG09; /* 49 */
    __RW __u32 ICFG10; /* 4a */
    __RW __u32 ICFG11; /* 4b */
    __RW __u32 ICFG12; /* 4c */
    __RW __u32 ICFG13; /* 4d */
    __RW __u32 ICFG14; /* 4e */
    __RW __u32 ICFG15; /* 4f */

    __RW __u32 ICFG16; /* 50 */
    __RW __u32 ICFG17; /* 51 */
    __RW __u32 ICFG18; /* 52 */
    __RW __u32 ICFG19; /* 53 */
    __RW __u32 ICFG20; /* 54 */
    __RW __u32 ICFG21; /* 55 */
    __RW __u32 ICFG22; /* 56 */
    __RW __u32 ICFG23; /* 57 */
    __RW __u32 ICFG24; /* 58 */
    __RW __u32 ICFG25; /* 59 */
    __RW __u32 ICFG26; /* 5a */
    __RW __u32 ICFG27; /* 5b */
    __RW __u32 ICFG28; /* 5c */
    __RW __u32 ICFG29; /* 5d */
    __RW __u32 ICFG30; /* 5e */
    __RW __u32 ICFG31; /* 5f */

    __RO __u32 IPND0;                      /* 60 */
    __RO __u32 IPND1;                      /* 61 */
    __RO __u32 IPND2;                      /* 62 */
    __RO __u32 IPND3;                      /* 63 */
    __RO __u32 IPND4;                      /* 64 */
    __RO __u32 IPND5;                      /* 65 */
    __RO __u32 IPND6;                      /* 66 */
    __RO __u32 IPND7;                      /* 67 */
    __WO __u32 ILAT_SET;                   /* 68 */
    __WO __u32 ILAT_CLR;                   /* 69 */
    __RW __u32 IPMASK;                     /* 6a */
    __RO __u32 REV_70_6a[0x70 - 0x6a - 1]; /*    */

    __RW __u32 ETM_CON;  /* 70 */
    __RO __u32 ETM_PC0;  /* 71 */
    __RO __u32 ETM_PC1;  /* 72 */
    __RO __u32 ETM_PC2;  /* 73 */
    __RO __u32 ETM_PC3;  /* 74 */
    __RW __u32 WP0_ADRH; /* 75 */
    __RW __u32 WP0_ADRL; /* 76 */
    __RW __u32 WP0_DATH; /* 77 */
    __RW __u32 WP0_DATL; /* 78 */
    __RW __u32 WP0_PC;   /* 79 */
} JL_TypeDef_q32DSP;

#undef __RW
#undef __RO
#undef __WO

#undef __u8
#undef __u16
#undef __u32

typedef struct _CPU_REGS {
    unsigned int reti;
    unsigned int rets;
    unsigned int psr;
    unsigned int r0;
    unsigned int r1;
    unsigned int r2;
    unsigned int r3;
    unsigned int r4;
    unsigned int r5;
    unsigned int r6;
    unsigned int r7;
    unsigned int r8;
    unsigned int r9;
    unsigned int r10;
    unsigned int r11;
    unsigned int r12;
    unsigned int r13;
    unsigned int r14;
    unsigned int r15;
} CPU_REGS;

#define TICK_CON                (q32DSP(0)->TTMR_CON)
#define TICK_PRD                (q32DSP(0)->TTMR_PRD)
#define TICK_CNT                (q32DSP(0)->TTMR_CNT)

#define SOFT_CLEAR_PENDING      (q32DSP(0)->ILAT_CLR)

#define CPU_MSG                 (q32DSP(0)->EMU_MSG)
#define CPU_CON                 (q32DSP(0)->EMU_CON)

#endif

//*********************************************************************************//
//                                                                                 //
//                               end of this module                                //
//                                                                                 //
//*********************************************************************************//
